The present disclosure relates to semiconductor device fabrication, and more particularly to a method of forming a gate spacer that can resist a long overetch that is required to form the gate spacers in fin field effect transistors (FinFETs) during a replacement gate scheme.
Field-effect transistors (FETs) generate an electric field by a gate structure to control the conductivity of a channel between a source region and a drain region in a semiconductor substrate. The gate of a finFET, and in some non-finFETs, may be formed by a replacement gate process in which a sacrificial gate, typically made of polysilicon, is removed to form a gate cavity, and gate materials replace the removed sacrificial gate material in the gate cavity.
During the fabrication of the FETs, the sacrificial gate is exposed to various etchants and cleaning chemistries. To protect the sacrificial gate, a spacer material is conformally applied to the sacrificial gate and then partially removed to form a gate spacer on a sidewall of the sacrificial gate. A problem arises in the prior art spacer formation in finFETs because the spacer etch in FinFETs has a huge build-in overetch budge in order to clear spacer material from fin sidewalls. This overetch that clears the sidewalls of fins also consumes the spacer material on the sidewalls of the sacrificial gate, which in turn, exposes polysilicon from the sacrificial gate at the polysilicon line ends. If polysilicon is exposed, epitaxial growth will also occur on the sacrificial gate. The uncontrolled epitaxial growth on the sacrificial gate can cause shorts of the polysilicon-polysilicon and polysilicon-contact. As such, a method to form a robust gate spacer that can resist the long overetch process in FinFETs is needed.